1. Technical Field
The present disclosure generally relates to an electronic device for generating a fractional frequency. More particularly, the present disclosure relates to a phase-switching fractional frequency synthesizer with reduction of the spurious fractional modulations.
2. Description of the Related Art
Electronic circuits are known, for generating an output signal at a desired frequency (referred to hereinafter as a “synthesized frequency”) which is a multiple of an input reference frequency: such devices are commonly indicated with frequency synthesizers.
Fractional frequency synthesizers are a particular class wherein the synthesized frequency is not an integer multiple of the reference frequency, but it is a fractional multiple of the reference frequency: for example, the synthesized frequency is 100, 25 times the reference frequency.
FIG. 1 schematically shows a possible implementation of a fractional frequency synthesizer 1 according to the prior art, implemented with a phase-locked loop. In particular, the fractional frequency synthesizer is of the phase-switching type: the controlled oscillator 12 generates a periodic signal S6 at a variable frequency and from the signal a plurality of signals, phase-shifted each other and at the same frequency f1 as the signal S6, are obtained, by means of a multi-phase generator 13; for example, FIG. 1 shows that four signals are obtained S1φ=0°, S2φ=90°, S3φ=180°, S4φ=270°, phase-shifted by φ=0°, φ=90°, φ=180°, φ=270° with respect to signal S6 generated by the controlled oscillator 12. Subsequently, by means of the parallel-serial phase selector 14, at least part of the signals phase-shifted by φ=0°, φ=90°, φ=180°, φ=270° are cyclically selected, by means of the logic circuit 16, according to the desired (fractional) synthesized frequency f1. In this way a synthesized signal S6 at a frequency f1 can be obtained, which is a fractional multiple of the reference frequency f0 of the signal S11, i.e. f1=(N+k/4)*f0, wherein N is the integer division factor of the frequency divider 15 and k is an integer number comprised between 0 and 3: in this case the minimum change in the synthesized frequency f1, which can be obtained with k=1, is equal to f0/4.
For example, FIG. 2a shows the case wherein the division factor of the frequency divider 15 is N=1 and the sequence of the selected phase-shifted signals is {S1, S2, S3, S4}, cyclically repeated. In this example the signal S10 has a fractional period equal to 5/4 times the period of the signal S6, i.e. it has a frequency equal to ⅘ times the frequency of S6.
A phase-switching fractional frequency synthesizer has the disadvantage that it generates not only a signal at the desired synthesized frequency, but it also adds spectral components at undesired frequencies (indicated with fractional spurious frequencies) near the synthesized frequency. This is due to the fact that it's not possible to obtain the plurality of signals phase-shifted each other with an absolute accuracy, but there is some inaccuracy between the phase-shifted signal edges. For example, FIG. 2a shows the case wherein four signals S1, S2, S3, S4 are generated phase-shifted by φ=0°, φ=90°, φ=180°, φ=270° in the ideal case and FIG. 2b in the real case: it can be observed that in the real case there is a shift by Δt of the edge of the pulses of the 90° phase-shifted signal. Consequently, signal S10 generated in the real case has a fundamental component (i.e. the desired one) at a frequency equal to ⅘ times the frequency of S6, but it also has an undesired phase shift keying at a frequency equal to ⅕ times the frequency of S6.
More generally, if the sequence of cyclic selection (also referred to as “rotation sequence”) of the phase-shifted signals S1, S2, S3, S4 is chosen so that the frequency of S10 is 1/(N+k/M) times the frequency of S6 (wherein N and M are integer numbers and wherein k=0, 1, . . . M−1), the signal S10 has an undesired phase shift keying at a frequency equal to 1/(N+k/M) times the frequency of S6.
It can occur that the fractional spurious frequencies get closer to the synthesized frequency when the required resolution increases (i.e. in case wherein the fractional part is smaller, i.e. when M increases) and therefore they cannot be easily eliminated by a filter.
Several techniques are known for filtering the fractional spurious frequencies, for example the document IEEE Journal of Solid-State Circuitis, vol. 36, n. 5, May 2001, pp. 777-783 by Chan-Hong Park et al. and the U.S. Pat. No. 7,298,809 e U.S. Pat. No. 7,298,790. These prior arts try to obtain a calibration of the plurality of phases, in order to keep the edges of the phase-shifted signals aligned with respect to the edges of a reference signal of the phase-locked loop and have the disadvantage that they require a plurality of additional loop filters and a plurality of tunable phase-shifters, which excessively increase the synthesizer complexity and the area occupation, especially in case of an implementation into an integrated circuit.